C8051F93X Datasheet, PDF (124/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 10.3. EMI0TC: External Memory Timing Control
Bit
7
6
5
4
3
2
Name
EAS[1:0]
EWR[3:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xAF
Bit
Name
Function
7:4
EAS Address Setup Time Select Bits.
Controls the timing parameter T_ACS.
00: Address Setup Time = 0 SYSCLK cycles.
01: Address Setup Time = 1 SYSCLK cycles.
10: Address Setup Time = 2 SYSCLK cycles.
11: Address Setup Time = 3 SYSCLK cycles.
3:2
EWR RD and WR Pulse Width Select.
Controls the timing parameter T_ACW.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
1:0
EAH Address Hold Time Select Bits.
Controls the timing parameter T_ACH.
00: Address Hold Time = 0 SYSCLK cycles.
01: Address Hold Time = 1 SYSCLK cycles.
10: Address Hold Time = 2 SYSCLK cycles.
11: Address Hold Time = 3 SYSCLK cycles.
1
0
EAH[1:0]
R/W
R/W
1
1
124
Rev. 1.3