C8051F93X Datasheet, PDF (61/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 4.9. ADC0 Electrical Characteristics
V_DD = 1.8 to 3.6V V, VREF = 1.65 V (REFSL[1:0] = 11), –40 to +85 °C unless otherwise specified.
Parameter
Resolution
Conditions
DC Accuracy
Min Typ Max Units
10
bits
Integral Nonlinearity
—
±0.5
±1
LSB
Differential Nonlinearity
Guaranteed Monotonic
—
±0.5
±1
LSB
Offset Error
—
±<1
±2
LSB
Full Scale Error
—
±1
±2.5
LSB
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 300 ksps)
Signal-to-Noise Plus Distortion
54
58
—
dB
Signal-to-Distortion
—
73
—
dB
Spurious-Free Dynamic Range
—
75
—
dB
SAR Conversion Clock
Conversion Rate
—
—
7.33 MHz
Conversion Time in SAR Clocks
10-bit Mode
8-bit Mode
13
—
— clocks
11
—
—
Track/Hold Acquisition Time
1.5
—
—
µs
Throughput Rate
—
—
300 ksps
Analog Inputs
ADC Input Voltage Range
Single Ended (AIN+ – GND)
0
— VREF
V
Absolute Pin Voltage with respect
to GND
Single Ended
0
—
V_DD
V
Sampling Capacitance
1x Gain
0.5x Gain
—
30
—
pF
28
Input Multiplexer Impedance
—
5
—
k
Power Supply Current 
(V_DD supplied to ADC0)
Power Supply Rejection
Power Specifications
Conversion Mode (300 ksps)
—
800
—
µA
Tracking Mode (0 ksps)
—
680
—
Internal High Speed VREF
External VREF
—
67
—
dB
—
74
—
Rev. 1.3
61