C8051F93X Datasheet, PDF (329/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Revision 1.2 to Revision 1.3
 Added labels to indicate center pad as “GND (optional)” to pinout diagrams in Figure 3.1 and
Figure 3.2.
 Added package marking diagrams as Figure 3.4, Figure 3.5, and Figure 3.6 to help identify the silicon
revision.
 Clarified conditions that apply to ‘VBAT Ramp Time for Power On’ for one-cell mode vs two-cell mode in
Table 4.4, “Reset Electrical Characteristics,” on page 59.
 Updated Section “5.2.3. Burst Mode” on page 71 and Figure 5.3 to show difference in behavior
between internal convert start signals and external CNVSTR signal.
 Added note about the need to ground the ADC mux before switching to the temperature sensor in
Section “5.6. Temperature Sensor” on page 86 and in SFR Definition 5.12 “ADC0MX”.
 Updated Figure 7.4, “CPn Multiplexer Block Diagram,” to show CPnOUT pull-up voltage (inverted)and
to correct the locations of VDD/DC+, VBAT, Digital Supply, and GND multiplexer inputs.
 Updated Table 8.1 to correct number of clock cycles for ‘CJNE A, direct, rel’.
 Corrected VDD ramp time reference in item 2 of Section “13.5.1. VDD Maintenance and the VDD
Monitor” on page 153.
 Updated CPT0WK bit description in SFR Definition 14.1, “PMU0CF”.
 Added Section “15.2. 32-bit CRC Algorithm” on page 169 to illustrate the 32-bit CRC algorithm.
 Updated Section “21.1.3. Interfacing Port I/O to 5 V and 3.3 V Logic” on page 218 to include notes
about sizing external pull-up resistors and other related information when using multi-voltage
interfaces.
 Corrected clock sources associated with T3XCLK settings in Section “25.3.2. 8-bit Timers with Auto-
Reload” on page 300, Figure 25.7, Figure 25.8, and Figure 25.9 to match the description in SFR
Definition 25.13.
 Removed ‘SmaRTClock divided by 8’ from list of possible clock sources in text description in Section
“26. Programmable Counter Array” on page 305.
 Replaced incorrect PCA channel references from PCA0CPH2 to PCA0CPH5 in Section
“26.4. Watchdog Timer Mode” on page 316 and Figure 26.11.
Rev. 1.3
329