C8051F93X Datasheet, PDF (291/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 25.4. TL0: Timer 0 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
TL0[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8A
Bit Name
Function
7:0 TL0[7:0] Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
SFR Definition 25.5. TL1: Timer 1 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
TL1[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8B
Bit Name
Function
7:0 TL1[7:0] Timer 1 Low Byte.
The TL1 register is the low byte of the 16-bit Timer 1.
Rev. 1.3
291