C8051F93X Datasheet, PDF (204/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 20.1. RTC0KEY: SmaRTClock Lock and Key
Bit
7
6
5
4
3
2
1
0
Name
RTC0ST[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAE
Bit Name
Function
7:0 RTC0ST SmaRTClock Interface Lock/Key and Status.
Locks/unlocks the SmaRTClock interface when written. Provides lock status when
read.
Read:
0x00: SmaRTClock Interface is locked.
0x01: SmaRTClock Interface is locked.
First key code (0xA5) has been written, waiting for second key code.
0x02: SmaRTClock Interface is unlocked.
First and second key codes (0xA5, 0xF1) have been written.
0x03: SmaRTClock Interface is disabled until the next system reset.
Write:
When RTC0ST = 0x00 (locked), writing 0xA5 followed by 0xF1 unlocks the
SmaRTClock Interface.
When RTC0ST = 0x01 (waiting for second key code), writing any value other
than the second key code (0xF1) will change RTC0STATE to 0x03 and disable
the SmaRTClock Interface until the next system reset.
When RTC0ST = 0x02 (unlocked), any write to RTC0KEY will lock the SmaRT-
Clock Interface.
When RTC0ST = 0x03 (disabled), writes to RTC0KEY have no effect.
204
Rev. 1.3