C8051F93X Datasheet, PDF (24/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
ADC0MX
P0.0
P2.6*
Temp
Sensor
VBAT
Digital Supply
VDD/ DC+
AMUX
Programmable
Attenuator
AIN+ _ADC0
Gain = 0. 5 or1
*P1.7-P2. 6 only available as
inputs on 32- pin packages
Figure 1.8. ADC0 Multiplexer Block Diagram
1.6. Programmable Current Reference (IREF0)
C8051F93x-C8051F92x devices include an on-chip programmable current reference (source or sink) with
two output current settings: low power mode and high current mode. The maximum current output in low
power mode is 63 µA (1 µA steps) and the maximum current output in high current mode is 504 µA (8 µA
steps).
1.7. Comparators
C8051F93x-C8051F92x devices include two on-chip programmable voltage comparators: Comparator 0
(CPT0) which is shown in Figure 1.9; Comparator 1 (CPT1) which is shown in Figure 1.10. The two
comparators operate identically but may differ in their ability to be used as reset or wake-up sources. See
Section “18. Reset Sources” on page 184 and the Section “14. Power Management” on page 159 for
details on reset sources and low power mode wake-up sources, respectively.
The Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an
asynchronous “raw” output (CP0A, CP1A). The asynchronous CP0A signal is available even when the
system clock is not active. This allows the Comparator to operate and generate an output when the device
is in some low power modes.
The comparator inputs may be connected to Port I/O pins or to other internal signals. Port pins may also be
used to directly sense capacitive touch switches.
24
Rev. 1.3