C8051F93X Datasheet, PDF (127/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
10.8.2.1.Multiplexed 8-bit MOVX with Bank Select: EMI0CF[3:2] = 10.
Muxed 8-bit WRITE with Bank Select
ADDR[11:8]
EMIF ADDRESS (4 MSBs) from EMI0CN
AD[7:0]
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
EMIF WRITE DATA
ALE
/WR
T
ACS
T
WDS
T
ACW
T
WDH
T
ACH
/RD
ADDR[11:8]
Muxed 8-bit READ with Bank Select
EMIF ADDRESS (4 MSBs) from EMI0CN
AD[7:0]
ALE
EMIF ADDRESS (8 LSBs) from
R0 or R1
T
ALEH
T
ALEL
EMIF READ DATA
T
RDS
T
RDH
ADDR[11:8]
AD[7:0]
ALE
/WR
/RD
ADDR[11:8]
AD[7:0]
ALE
T_ACS
T_ACW
T_ACH
/RD
/RD
/WR
/WR
Note: See the Port Input/Output chapter to determine which port pins are mapped to the
ADDR[11:8], AD[7:0], ALE, /RD, and /WR signals.
Figure 10.6. Multiplexed 8-bit MOVX with Bank Select Timing
Rev. 1.3
127