C8051F93X Datasheet, PDF (268/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
24. Enhanced Serial Peripheral Interface (SPI0 and SPI1)
The Enhanced Serial Peripheral Interfaces (SPI0 and SPI1) provide access to two identical, flexible, full-
duplex synchronous serial busses. Both SPI0 and SPI1 will be referred to collectively as SPIn. SPIn can
operate as a master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and
slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input to select SPIn in
slave mode, or to disable Master Mode operation in a multi-master environment, avoiding contention on
the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional general
purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SPInCKR
SPInCFG
SPInCN
SYSCLK
Clock Divide
Logic
SPI CONTROL LOGIC
Data Path
Control
Pin Interface
Control
SPIn IRQ
Tx Data
MOSI
C
SPInDAT
Transmit Data Buffer
SCK ^R
O
Shift Register
76543210
Rx Data
Pin
Control
Logic
MISO
S
S
B
A
R
Receive Data Buffer
NSS
Write
SPI0DAT
Read
SPI0DAT
SFR Bus
Figure 24.1. SPI Block Diagram
Port I/O
268
Rev. 1.3