C8051F93X Datasheet, PDF (214/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration
Bit
7
6
5
4
3
2
1
0
Name AUTOSTP LOADRDY
Type
R/W
R
R
Reset
0
0
0
LOADCAP
R
R/W
0
Varies Varies Varies Varies
SmaRTClock Address = 0x06
Bit
Name
Function
7 AUTOSTP Automatic Load Capacitance Stepping Enable.
Enables/disables automatic load capacitance stepping.
0: Load capacitance stepping disabled.
1: Load capacitance stepping enabled.
6 LOADRDY Load Capacitance Ready Indicator.
Set by hardware when the load capacitance matches the programmed value.
0: Load capacitance is currently stepping.
1: Load capacitance has reached it programmed value.
5:4
Unused Unused.
Read = 00b; Write = Don’t Care.
3:0 LOADCAP Load Capacitance Programmed Value.
Holds the user’s desired value of the load capacitance. See Table 20.2 on
page 207.
Internal Register Definition 20.7. RTC0PIN: SmaRTClock Pin Configuration
Bit
7
6
5
4
3
2
1
0
Name
RTC0PIN
Type
W
Reset
0
1
1
0
0
1
1
1
SmaRTClock Address = 0x07
Bit Name
Function
7:0 RTC0PIN SmaRTClock Pin Configuration.
Writing 0xE7 to this register forces XTAL3 and XTAL4 to be internally shorted for use
with Self Oscillate Mode.
Writing 0x67 returns XTAL3 and XTAL4 to their normal configuration.
214
Rev. 1.3