C8051F93X Datasheet, PDF (260/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
23. UART0
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART.
Enhanced baud rate support allows a wide range of clock sources to generate standard baud rates (details
in Section “23.1. Enhanced Baud Rate Generation” on page 261). Received data buffering allows UART0
to start reception of a second incoming data byte before software has finished reading the previous data
byte.
UART0 has two associated SFRs: Serial Control Register 0 (SCON0) and Serial Data Buffer 0 (SBUF0).
The single SBUF0 location provides access to both transmit and receive registers. Writes to SBUF0
always access the Transmit register. Reads of SBUF0 always access the buffered Receive register;
it is not possible to read data from the Transmit register.
With UART0 interrupts enabled, an interrupt is generated each time a transmit is completed (TI0 is set in
SCON0), or a data byte has been received (RI0 is set in SCON0). The UART0 interrupt flags are not
cleared by hardware when the CPU vectors to the interrupt service routine. They must be cleared manually
by software, allowing software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF
TB8
SET
D
Q
CLR
SBUF
(TX Shift)
Zero Detector
Stop Bit
Start
Tx Clock
Shift
Tx Control
Data
Tx IRQ ^Send
TX _Crossbar
UART Baud
Rate Generator
SCON
TI
Serial
Port
Interrupt
RI
Port I/O
Rx Clock
Start
Shift
Rx IRQ
Rx Control
0x1FF
RB8
Load
SBUF
Input Shift Register
(9 bits)
Load SBUF
SBUF
(RX Latch)
Read
SBUF
SFR Bus
RX _Crossbar
Figure 23.1. UART0 Block Diagram
260
Rev. 1.3