C8051F93X Datasheet, PDF (264/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Master
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
RX
TX
Slave
Device
V+
RX
TX
Figure 23.6. UART Multi-Processor Mode Interconnect Diagram
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Rev. 1.3