C8051F93X Datasheet, PDF (267/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 23.1. Timer Settings for Standard Baud Rates
Using The Internal 24.5 MHz Oscillator
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
Baud Rate
% Error
–0.32%
–0.32%
0.15%
–0.32%
0.15%
–0.32%
–0.32%
0.15%
Frequency: 24.5 MHz
Oscilla- Timer Clock
tor Divide Source
Factor
SCA1–SCA0
(pre-scale
select)¹
106
SYSCLK
XX²
212
SYSCLK
XX
426
SYSCLK
XX
848
SYSCLK/4
01
1704 SYSCLK/12
00
2544 SYSCLK/12
00
10176 SYSCLK/48
10
20448 SYSCLK/48
10
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 25.1.
2. X = Don’t care.
T1M^{1 Timer 1}
Reload
Value (hex)
1
0xCB
1
0x96
1
0x2B
0
0x96
0
0xB9
0
0x96
0
0x96
0
0x2B
Table 23.2. Timer Settings for Standard Baud Rates
Using an External 22.1184 MHz Oscillator
Target
Baud Rate
(bps)
230400
115200
57600
28800
14400
9600
2400
1200
230400
115200
57600
28800
14400
9600
Baud Rate
% Error
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
0.00%
Frequency: 22.1184 MHz
Oscilla- Timer Clock
tor Divide Source
Factor
SCA1–SCA0
(pre-scale
select)¹
96
SYSCLK
XX²
192
SYSCLK
XX
384
SYSCLK
XX
768 SYSCLK / 12
00
1536 SYSCLK / 12
00
2304 SYSCLK / 12
00
9216 SYSCLK / 48
10
18432 SYSCLK / 48
10
96
EXTCLK / 8
11
192
EXTCLK / 8
11
384
EXTCLK / 8
11
768
EXTCLK / 8
11
1536 EXTCLK / 8
11
2304 EXTCLK / 8
11
Notes:
1. SCA1–SCA0 and T1M bit definitions can be found in Section 25.1.
2. X = Don’t care.
T1M^{1 Timer 1}
Reload
Value (hex)
1
0xD0
1
0xA0
1
0x40
0
0xE0
0
0xC0
0
0xA0
0
0xA0
0
0x40
0
0xFA
0
0xF4
0
0xE8
0
0xD0
0
0xA0
0
0x70
Rev. 1.3
267