C8051F93X Datasheet, PDF (162/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
14.4. Suspend Mode
Setting the Suspend Mode Select bit (PMU0CF.6) causes the system clock to be gated off and all internal
oscillators disabled. All digital logic (timers, communication peripherals, interrupts, CPU, etc.) stops
functioning until one of the enabled wake-up sources occurs.
Important Notes:
• When entering Suspend Mode, the global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
• The one-shot circuit should be enabled by clearing the BYPASS bit (FLSCL.6) to logic 0. See
the note in SFR Definition 13.3. FLSCL: Flash Scale for more information on how to properly
clear the BYPASS bit.
• Upon wake-up from suspend mode, PMU0 requires two system clocks in order to update the
PMU0CF wake-up flags. All flags will read back a value of '0' during the first two system clocks
following a wake-up from suspend mode.
The following wake-up sources can be configured to wake the device from Suspend Mode:
• SmaRTClock Oscillator Fail
• SmaRTClock Alarm
• Port Match Event
• Comparator0 Rising Edge
In addition, a noise glitch on RST that is not long enough to reset the device will cause the device to exit
suspend. In order for the MCU to respond to the pin reset event, software must not place the device back
into suspend mode for a period of 15 µs. The PMU0CF register may be checked to determine if the wake-
up was due to a falling edge on the /RST pin. If the wake-up source is not due to a falling edge on RST,
there is no time restriction on how soon software may place the device back into suspend mode. A 4.7 k
pullup resistor to VDD/DC+ is recommend for RST to prevent noise glitches from waking the device.
14.5. Sleep Mode
Setting the Sleep Mode Select bit (PMU0CF.6) turns off the internal 1.8 V regulator (VREG0) and switches
the power supply of all on-chip RAM to the VBAT pin (see Figure 14.1). Power to most digital logic on the
chip is disconnected; only PMU0 and the SmaRTClock remain powered. Analog peripherals remain
powered in two-cell mode and lose their supply in one-cell mode because the dc-dc converter is disabled.
In two-cell mode, only the Comparators remain functional when the device enters Sleep Mode. All other
analog peripherals (ADC0, IREF0, External Oscillator, etc.) should be disabled prior to entering Sleep
Mode.
Important Notes:
• When entering Sleep Mode, the global clock divider must be set to "divide by 1" by setting
CLKDIV[2:0] = 000b in the CLKSEL register.
• Per device errata, for Revision D and prior silicon, the CLKSEL register must select “low power
oscillator divided by 2” as the system clock source and wait for CLKRDY to be set prior to
entering Sleep Mode.
GPIO pins configured as digital outputs will retain their output state during sleep mode. In two-cell mode,
they will maintain the same current drive capability in sleep mode as they have in normal mode. In one-cell
mode, the VDD/DC+ supply will drop to the level of VBAT, which will reduce the output high-voltage level
and the source and sink current drive capability.
162
Rev. 1.3