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C8051F93X Datasheet, PDF (181/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks
C8051F93x-C8051F92x
16.9. DC-DC Converter Register Descriptions
The SFRs used to configure the dc-dc converter are described in the following register descriptions. The
reset values for these registers can be used as-is in most systems; therefore, no software intervention or
initialization is required.
SFR Definition 16.1. DC0CN: DC-DC Converter Control
Bit
7
6
5
4
3
2
1
0
Name
MINPW
SWSEL Reserved SYNC
VSEL
Type
R/W
R/W
R/W
R/W
R/W
Reset
0
0
1
0
0
0
0
1
SFR Page = 0x0; SFR Address = 0x97
Bit
Name
Function
7:6 MINPW[1:0] DC-DC Converter Minimum Pulse Width.
Specifies the minimum pulse width.
00: No minimum duty cycle.
01: Minimum pulse width is 20 ns.
10: Minimum pulse width is 40 ns.
11: Minimum pulse width is 80 ns.
5
SWSEL DC-DC Converter Switch Select.
Selects one of two possible converter switch sizes to maximize efficiency.
0: The large switches are selected (best efficiency for high output currents).
1: The small switches are selected (best efficiency for low output currents).
4
Reserved Reserved. Always Write to 0.
3
SYNC ADC0 Synchronization Enable.
When synchronization is enabled, the ADC0SC[4:0] bits in the ADC0CF register
must be set to 00000b. Behavior as described is valid in REVC and later devices.
0: The ADC is not synchronized to the dc-dc converter.
1: The ADC is synchronized to the dc-dc converter. ADC0 tracking is performed
during the longest quiet time of the dc-dc converter switching cycle and ADC0 SAR
clock is also synchronized to the dc-dc converter switching cycle.
2:0 VSEL[2:0] DC-DC Converter Output Voltage Select.
Specifies the target output voltage.
000: Target output voltage is 1.8 V.
001: Target output voltage is 1.9 V.
010: Target output voltage is 2.0 V.
011: Target output voltage is 2.1 V.
100: Target output voltage is 2.4 V.
101: Target output voltage is 2.7 V.
110: Target output voltage is 3.0 V.
111: Target output voltage is 3.3 V.
Rev. 1.3
181