C8051F93X Datasheet, PDF (212/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
Bit
Name
Type
Reset
7
RTC0EN
R/W
0
6
MCLKEN
R/W
0
5
OSCFAIL
R/W
Varies
4
RTC0TR
R/W
0
3
RTC0AEN
R/W
0
2
ALRM
R/W
0
1
0
RTC0SET RTC0CAP
R/W
R/W
0
0
SmaRTClock Address = 0x04
Bit Name
Function
7 RTC0EN SmaRTClock Enable.
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
6 MCLKEN Missing SmaRTClock Detector Enable.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
5 OSCFAIL SmaRTClock Oscillator Fail Event Flag.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be
cleared by software. The value of this bit is not defined when the SmaRTClock 
oscillator is disabled.
4 RTC0TR SmaRTClock Timer Run Control.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
3 RTC0AEN SmaRTClock Alarm Enable.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
2 ALRM SmaRTClock Alarm Event Read:
Write:
Flag and Auto Reset
0: SmaRTClock alarm
0: Disable Auto Reset.
Enable
event flag is de-asserted. 1: Enable Auto Reset.
Reads return the state of the ^{1: SmaRTClock alarm}
alarm event flag.
event flag is asserted.
Writes enable/disable the 
Auto Reset function.
1 RTC0SET SmaRTClock Timer Set.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hard-
ware to indicate that the timer set operation is complete.
0 RTC0CAP SmaRTClock Timer Capture.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by
hardware to indicate that the timer capture operation is complete.
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle. See Section “Power
Management” on page 159 for information on how to capture a SmaRTClock Alarm event using a flag which
is not automatically cleared by hardware.
212
Rev. 1.3