C8051F93X Datasheet, PDF (256/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled (EHACK = 0)
Values Read
Values to
Write
Current SMbus State
Typical Response Options
1110
0
0
X
A master START was gener-
ated.
Load slave address + R/W into
SMB0DAT.
0 0 X 1100
A master data or address byte Set STA to restart transfer.
0 0 0 was transmitted; NACK
received.
Abort transfer.
1 0 X 1110
01X -
Load next data byte into
SMB0DAT.
0 0 X 1100
1100
0
0
End transfer with STOP.
A master data or address byte End transfer with STOP and start
1 was transmitted; ACK
another transfer.
0
1
1
1
X
X
-
-
received.
Send repeated START.
1 0 X 1110
Switch to Master Receiver Mode
(clear SI without writing new data 0 0 X 1000
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
0 0 1 1000
Send NACK to indicate last byte,
and send STOP.
0
1
0
-
Send NACK to indicate last byte,
and send STOP followed by
1 1 0 1110
START.
1000
1
0
X
A master data byte was
received; ACK requested.
Send ACK followed by repeated
START.
1
0
1
1110
Send NACK to indicate last byte,
and send repeated START.
1
0
0
1110
Send ACK and switch to Master
Transmitter Mode (write to
0 0 1 1100
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to 0 0 0 1100
SMB0DAT before clearing SI).
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Rev. 1.3