C8051F93X Datasheet, PDF(13/330 Page) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93X Datasheet, PDF (13/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93x-C8051F92x

Table 22.2. Minimum SDA Setup and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . 244

Table 22.3. Sources for Hardware Changes to SMB0CN . . . . . . . . . . . . . . . . . . . 248

Table 22.4. Hardware Address Recognition Examples (EHACK = 1) . . . . . . . . . . 249

Table 22.5. SMBus Status Decoding With Hardware ACK Generation Disabled

(EHACK = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256

Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled

(EHACK = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Table 23.1. Timer Settings for Standard Baud Rates ï

Using The Internal 24.5 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . 267

Table 23.2. Timer Settings for Standard Baud Rates ï

Using an External 22.1184 MHz Oscillator . . . . . . . . . . . . . . . . . . . . . 267

Table 24.1. SPI Slave Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

Table 25.1. Timer 0 Running Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Table 26.1. PCA Timebase Input Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

Table 26.2. PCA0CPM and PCA0PWM Bit Settings for PCA Capture/Compare Mod-

ules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

Table 26.3. Watchdog Timer Timeout Intervals1 . . . . . . . . . . . . . . . . . . . . . . . . . . 317

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