C8051F93X Datasheet, PDF (286/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Pre-scaled C lock
SYSCLK
T0
C ro ss b a r
GATE0
CKCON
TTTTTTSS
3 3 2 2 1 0CC
MMMMMMA A
HLHL
10
TMOD
GCT TGCT T
A / 11A / 00
T TMM T TMM
E1 1 0E0 1 0
1
0
0
0
1
1
IT 0 1 C F
IIIIIIII
NNNNNNNN
11110000
PSSSPSSS
LLLLLLLL
210 210
TR0
TCLK
TL0
(5 bits)
TH0
(8 bits)
TF1
TR1
TF0
TR0
IE 1
IT 1
IE 0
IT 0
Interrupt
IN T 0
IN 0PL _XOR
Figure 25.1. T0 Mode 0 Block Diagram
25.1.2. Mode 1: 16-bit Counter/Timer
Mode 1 operation is the same as Mode 0, except that the counter/timer registers use all 16 bits. The
counter/timers are enabled and configured in Mode 1 in the same manner as for Mode 0.
286
Rev. 1.3