C8051F93X Datasheet, PDF (203/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
20.1.4. SmaRTClock Interface Autoread Feature
When Autoread is enabled, each read from RTC0DAT initiates the next indirect read operation on the
SmaRTClock internal register selected by RTC0ADR. Software should set the BUSY bit once at the
beginning of each series of consecutive reads. Software should follow recommended instruction timing or
check if the SmaRTClock Interface is busy prior to reading RTC0DAT. Autoread is enabled by setting
AUTORD (RTC0ADR.6) to logic 1.
20.1.5. RTC0ADR Autoincrement Feature
For ease of reading and writing the 32-bit CAPTURE and ALARM values, RTC0ADR automatically
increments after each read or write to a CAPTUREn or ALARMn register. This speeds up the process of
setting an alarm or reading the current SmaRTClock timer value. Autoincrement is always enabled.
Recommended Instruction Timing for a multi-byte register read with short strobe and autoread enabled:
mov RTC0ADR, #0d0h
nop
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
nop
nop
mov A, RTC0DAT
Recommended Instruction Timing for a multi-byte register write with short strobe enabled:
mov RTC0ADR, #010h
mov RTC0DAT, #05h
nop
mov RTC0DAT, #06h
nop
mov RTC0DAT, #07h
nop
mov RTC0DAT, #08h
nop
Rev. 1.3
203