C8051F93X Datasheet, PDF (190/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 18.2. RSTSRC: Reset Source
Bit
7
6
5
4
3
2
1
0
Name
Type
Reset
RTC0RE
R/W
Varies
FERROR
R
Varies
C0RSEF
R/W
Varies
SWRSF
R/W
Varies
WDTRSF MCDRSF
R
R/W
Varies
Varies
PORSF
R/W
Varies
PINRSF
R
Varies
SFR Page = 0x0; SFR Address = 0xEF.
Bit Name
Description
Write
Read
7 RTC0RE SmaRTClock Reset Enable 0: Disable SmaRTClock Set to 1 if SmaRTClock
and Flag
as a reset source.
alarm or oscillator fail
1: Enable SmaRTClock as caused the last reset.
a reset source.
6 FERROR Flash Error Reset Flag.
N/A
Set to 1 if Flash
read/write/erase error
caused the last reset.
5 C0RSEF Comparator0 Reset Enable 0: Disable Comparator0 as Set to 1 if Comparator0
and Flag.
a reset source.
caused the last reset.
1: Enable Comparator0 as
a reset source.
4 SWRSF Software Reset Force and Writing a 1 forces a sys- Set to 1 if last reset was
Flag.
tem reset.
caused by a write to
SWRSF.
3 WDTRSF Watchdog Timer Reset Flag. N/A
Set to 1 if Watchdog Timer
overflow caused the last
reset.
2 MCDRSF Missing Clock Detector
(MCD) Enable and Flag.
0: Disable the MCD.
1: Enable the MCD.
The MCD triggers a reset
if a missing clock condition
is detected.
Set to 1 if Missing Clock
Detector timeout caused
the last reset.
1 PORSF Power-On / Power-Fail
0: Disable the VDD/DC+ Set to 1 anytime a power-
Reset Flag, and Power-Fail
Reset Enable.
Supply Monitor as a reset
source.
oonccourrsV.^{D2 D monitor reset}
1: Enable the VDD/DC+
Supply Monitor as a reset
source.³
0 PINRSF HW Pin Reset Flag.
N/A
Set to 1 if RST pin caused
the last reset.
Notes:
1. It is safe to use read-modify-write operations (ORL, ANL, etc.) to enable or disable specific interrupt sources.
2. If PORSF read back 1, the value read from all other bits in this register are indeterminate.
3. Writing a 1 to PORSF before the VDD/DC+ Supply Monitor is stabilized may generate a system reset.
190
Rev. 1.3