C8051F93X Datasheet, PDF (125/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
10.8. EMIF Timing Diagrams
10.8.1. Multiplexed 16-bit MOVX: EMI0CF[3:2] = 01, 10, or 11
Muxed 16-bit WRITE
ADDR[11:8]
EMIF ADDRESS (4 MSBs) from DPH
AD[7:0]
EMIF ADDRESS (8 LSBs) from
DPL
T_ALEH
T_ALEL
EMIF WRITE DATA
ALE
/WR
T
ACS
T
WDS
T
ACW
T
WDH
T
ACH
/RD
Muxed 16-bit READ
ADDR[11:8]
EMIF ADDRESS (4 MSBs) from DPH
AD[7:0]
ALE
EMIF ADDRESS (8 LSBs) from
DPL
T
ALEH
T
ALEL
EMIF READ DATA
T
RDS
T
RDH
ADDR[11:8]
AD[7:0]
ALE
/WR
/RD
ADDR[11:8]
AD[7:0]
ALE
T
ACS
T
ACW
T
ACH
/RD
/RD
/WR
/WR
Note: See the Port Input/Output chapter to determine which port pins are mapped to the
ADDR[11:8], AD[7:0], ALE, /RD, and /WR signals.
Figure 10.4. Multiplexed 16-bit MOVX Timing
Rev. 1.3
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