C8051F93X Datasheet, PDF (47/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 4.2. Global Electrical Characteristics (Continued)
–40 to +85 °C, 25 MHz system clock unless otherwise specified. See "AN358: Optimizing Low Power Operation of the
‘F9xx" for details on how to achieve the supply current specifications listed in this table.
Parameter
Conditions
Min Typ Max Units
Digital Supply Current—Suspend and Sleep Mode
Digital Supply Current⁶ 
(Suspend Mode)
V_DD = 1.8–3.6 V, two-cell mode
— 77 —
µA
Digital Supply Current
1.8 V, T = 25 °C
— 0.60 —
µA
(Sleep Mode, SmaRTClock 3.0 V, T = 25 °C
— 0.75 —
µA
running)
3.6 V, T = 25 °C
— 0.85 —
µA
1.8 V, T = 85 °C
— 1.30 —
µA
3.0 V, T = 85 °C
— 1.60 —
µA
3.6 V, T = 85 °C
— 1.90 —
µA
(includes SmaRTClock oscillator and VBAT
Supply Monitor)
Digital Supply Current
(Sleep Mode)
1.8 V, T = 25 °C
3.0 V, T = 25 °C
3.6 V, T = 25 °C
1.8 V, T = 85 °C
3.0 V, T = 85 °C
3.6 V, T = 85 °C
(includes VBAT supply monitor)
— 0.05 —
µA
— 0.08 —
µA
— 0.12 —
µA
— 0.75 —
µA
— 0.90 —
µA
— 1.20 —
µA
Notes:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with
the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3
CPU clock cycles, and the Flash memory is read on each cycle. The supply current will vary slightly based on the
physical location of the sjmp instruction and the number of Flash address lines that toggle as a result. In the worst
case, current can increase by up to 30% if the sjmp loop straddles a 128-byte Flash address boundary (e.g.,
0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across
the 128-byte address boundaries.
4. Includes oscillator and regulator supply current.
5. IDD can be estimated for frequencies <10 MHz by simply multiplying the frequency of interest by the frequency
sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to estimate I_DD for
>10 MHz, the estimate should be the current at 25 MHz minus the difference in current indicated by the frequency
sensitivity number. For example: V_DD = 3.0 V; F = 20 MHz, I_DD = 4.1 mA – (25 MHz –
20 MHz) x 0.120 mA/MHz = 3.5 mA.
6. The supply current specifications in Table 4.2 are for two cell mode. The VBAT current in one-cell mode can be
estimated using the following equation:
VBAT Current (one-cell mode) = --^S----^u-_D--^p--_C--^p--_--^l-_D-^y----_CV----^o--_C--^l-^t-_o-^a--_n-^g---_ve---_e--^-_r--_t--_eS---_r-^u---_Ep----^pf-_f--^li-^yc---_i--_eC---_n-^u--_c--^r-_y-^r--^e--_-ⁿ---^t-_V---⁽-_B-^t-^w--_A---^o-_T--^---^c-_V--^e--_o-^l--^ll--_t-^ma----_g-^o--_e-^d---^e----⁾
The VBAT Voltage is the voltage at the VBAT pin, typically 0.9 to 1.8 V.
The Supply Current (two-cell mode) is the data sheet specification for supply current.
The Supply Voltage is the voltage at the VDD/DC+ pin, typically 1.8 to 3.3 V (default = 1.9 V).
The DC-DC Converter Efficiency can be estimated using Figure 4.3–Figure 4.5.
7. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the
frequency sensitivity number. For example: V_DD = 3.0 V; F = 5 MHz, Idle I_DD = 2.5 mA – (25 MHz –
5 MHz) x 0.095 mA/MHz = 0.6 mA.
Rev. 1.3
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