C8051F93X Datasheet, PDF (78/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
Bit
7
6
5
4
3
2
1
0
Name Reserved
AD0PWR[3:0]
Type
R
R
R
R
R/W
Reset
0
0
0
0
1
1
1
1
SFR Page = 0xF; SFR Address = 0xBA
Bit
Name
Function
7
Reserved Reserved.
Read = 0b; Must write 0b.
6:4
Unused Unused.
Read = 0000b; Write = Don’t Care.
3:0 AD0PWR[3:0] ADC0 Burst Mode Power-Up Time.
Sets the time delay required for ADC0 to power up from a low power state.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1:
ADC0 remains enabled and does not enter a low power state after all conver-
sions are complete.
Conversions can begin immediately following the start-of-conversion signal.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters a low power state (as specified in Table 5.1) after all conversions
are complete. 
Conversions can begin a programmed delay after the start-of-conversion sig-
nal.
The ADC0 Burst Mode Power-Up time is programmed according to the follow-
ing equation:
AD0PWR
=
T_----s_---t_--a_---r_---t_--u_---p_--
400ns
–
1
or
Tstartup = AD0PWR + 1400ns
78
Rev. 1.3