C8051F93X Datasheet, PDF (145/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
Bit
7
6
5
4
3
2
1
0
Name
PSPI1 PRTC0F PMAT PWARN
Type
R
R
R
R
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = All Pages; SFR Address = 0xF7
Bit Name
Function
7:4 Unused Unused.
Read = 0000b. Write = Don’t care.
3 PSPI1 Serial Peripheral Interface (SPI1) Interrupt Priority Control.
This bit sets the priority of the SPI1 interrupt.
0: SP1 interrupt set to low priority level.
1: SPI1 interrupt set to high priority level.
2 PRTC0F SmaRTClock Oscillator Fail Interrupt Priority Control.
This bit sets the priority of the SmaRTClock Alarm interrupt.
0: SmaRTClock Alarm interrupt set to low priority level.
1: SmaRTClock Alarm interrupt set to high priority level.
1 PMAT Port Match Interrupt Priority Control.
This bit sets the priority of the Port Match Event interrupt.
0: Port Match interrupt set to low priority level.
1: Port Match interrupt set to high priority level.
0 PWARN VDD/DC+ Supply Monitor Early Warning Interrupt Priority Control.
This bit sets the priority of the VDD/DC+ Supply Monitor Early Warning interrupt.
0: VDD/DC+ Supply Monitor Early Warning interrupt set to low priority level.
1: VDD/DC+ Supply Monitor Early Warning interrupt set to high priority level.
Rev. 1.3
145