C8051F93X Datasheet, PDF (158/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 13.3. FLSCL: Flash Scale
Bit
7
6
5
4
3
2
1
0
Name
BYPASS
Type
R
R/W
R
R
R
R
R
R
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xB6
Bit Name
Function
7 Reserved Reserved. Always Write to 0.
6 BYPASS Flash Read Timing One-Shot Bypass.
0: The one-shot determines the Flash read time. This setting should be used for oper-
ating frequencies less than 10 MHz.
1: The system clock determines the Flash read time. This setting should be used for
frequencies greater than 10 MHz.
5:0 Reserved Reserved. Always Write to 000000.
Note: When changing the BYPASS bit from 1 to 0, the third opcode byte fetched from program memory is
indeterminate. Therefore, the operation which clears the BYPASS bit should be immediately followed by a
benign 3-byte instruction whose third byte is a don’t care. An example of such an instruction is a 3-byte MOV
that targets the FLWR register. When programming in ‘C’, the dummy value written to FLWR should be a non-
zero value to prevent the compiler from generating a 2-byte MOV instruction.
SFR Definition 13.4. FLWR: Flash Write Only
Bit
7
6
5
4
3
2
1
0
Name
FLWR[7:0]
Type
W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xE5
Bit Name
Function
7:0 FLWR[7:0] Flash Write Only.
All writes to this register have no effect on system operation.
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Rev. 1.3