C8051F93X Datasheet, PDF (205/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 20.2. RTC0ADR: SmaRTClock Address
Bit
7
6
5
4
3
2
1
0
Name BUSY AUTORD
SHORT
ADDR[3:0]
Type
R/W
R/W
R
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xAC
Bit Name
Function
7
BUSY SmaRTClock Interface Busy Indicator.
Indicates SmaRTClock interface status. Writing 1 to this bit initiates an indirect read.
6 AUTORD SmaRTClock Interface Autoread Enable.
Enables/disables Autoread.
0: Autoread Disabled.
1: Autoread Enabled.
5
Unused Unused. Read = 0b; Write = Don’t Care.
4
SHORT Short Strobe Enable.
Enables/disables the Short Strobe Feature.
0: Short Strobe disabled.
1: Short Strobe enabled.
3:0 ADDR[3:0] SmaRTClock Indirect Register Address.
Sets the currently selected SmaRTClock register.
See Table 20.1 for a listing of all SmaRTClock indirect registers.
Note: The ADDR bits increment after each indirect read/write operation that targets a CAPTUREn or ALARMn
internal SmaRTClock register.
SFR Definition 20.3. RTC0DAT: SmaRTClock Data
Bit
7
6
5
4
3
2
1
0
Name
RTC0DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xAD
Bit Name
Function
7:0 RTC0DAT SmaRTClock Data Bits.
Holds data transferred to/from the internal SmaRTClock register selected by
RTC0ADR.
Note: Read-modify-write instructions (orl, anl, etc.) should not be used on this register.
Rev. 1.3
205