C8051F93X Datasheet, PDF (67/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
5. 10-Bit SAR ADC with 16-bit Auto-Averaging Accumulator and
Autonomous Low Power Burst Mode
The ADC0 on the C8051F93x-C8051F92x is a 300 ksps, 10-bit successive-approximation-register (SAR)
ADC with integrated track-and-hold and programmable window detector. ADC0 also has an autonomous
low power Burst Mode which can automatically enable ADC0, capture and accumulate samples, then
place ADC0 in a low power shutdown mode without CPU intervention. It also has a 16-bit accumulator that
can automatically oversample and average the ADC results.
The ADC is fully configurable under software control via Special Function Registers. The ADC0 operates in
Single-ended mode and may be configured to measure various different signals using the analog multi-
plexer described in “5.5. ADC0 Analog Multiplexer” on page 84. The voltage reference for the ADC is
selected as described in “5.7. Voltage and Ground Reference Options” on page 89.
ADC0CN
ADC0TK
ADC0PWR
Burst Mode Logic
From
AMUX0
AIN+
VDD
10-Bit
SAR
ADC
000
Start
Conversion
001
010
011
100
AD0BUSY (W)
Timer 0 Overflow
Timer 2 Overflow
Timer 3 Overflow
CNVSTR Input
16-Bit Accumulator
ADC0LTH ADC0LTL
AD0WINT
W indow
Compare
32
Logic
ADC0CF
ADC0GTH ADC0GTL
Figure 5.1. ADC0 Functional Block Diagram
Rev. 1.3
67