C8051F93X Datasheet, PDF (292/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 25.6. TH0: Timer 0 High Byte
Bit
7
6
5
4
3
2
1
0
Name
TH0[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8C
Bit Name
Function
7:0 TH0[7:0] Timer 0 High Byte.
The TH0 register is the high byte of the 16-bit Timer 0.
SFR Definition 25.7. TH1: Timer 1 High Byte
Bit
7
6
5
4
3
2
1
0
Name
TH1[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x8D
Bit Name
Function
7:0 TH1[7:0] Timer 1 High Byte.
The TH1 register is the high byte of the 16-bit Timer 1.
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Rev. 1.3