C8051F93X Datasheet, PDF (80/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 5.6. ADC0H: ADC0 Data Word High Byte
Bit
7
6
5
4
3
2
1
0
Name
ADC0[15:8]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBE
Bit Name
Description
Read
Write
7:0 ADC0[15:8] ADC0 Data Word High Byte. Most Significant Byte of the Set the most significant
16-bit ADC0 Accumulator byte of the 16-bit ADC0
formatted according to the Accumulator to the value
settings in AD0SJST[2:0]. written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be zeros. This register
should not be written when the SYNC bit is set to 1.
SFR Definition 5.7. ADC0L: ADC0 Data Word Low Byte
Bit
7
6
5
4
3
2
1
0
Name
ADC0[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xBD;
Bit Name
Description
Read
Write
7:0 ADC0[7:0] ADC0 Data Word Low Byte. Least Significant Byte of the Set the least significant
16-bit ADC0 Accumulator byte of the 16-bit ADC0
formatted according to the Accumulator to the value
settings in AD0SJST[2:0]. written.
Note: If Accumulator shifting is enabled, the most significant bits of the value read will be the least significant bits of
the accumulator high byte. This register should not be written when the SYNC bit is set to 1.
80
Rev. 1.3