C8051F93X Datasheet, PDF (265/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 23.1. SCON0: Serial Port 0 Control
Bit
7
6
5
4
3
2
1
0
Name S0MODE
Type
R/W
R
Reset
0
1
MCE0
REN0
TB80
RB80
TI0
RI0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x98; Bit-Addressable
Bit Name
Function
7 S0MODE ^{Serial Port 0 Operation Mode.}
Selects the UART0 Operation Mode.
0: 8-bit UART with Variable Baud Rate.
1: 9-bit UART with Variable Baud Rate.
6 Unused ^Unused.
Read = 1b. Write = Don’t Care.
5 MCE0 ^{Multiprocessor Communication Enable.}
For Mode 0 (8-bit UART): Checks for valid stop bit.
0: Logic level of stop bit is ignored.
1: RI0 will only be activated if stop bit is logic level 1.
For Mode 1 (9-bit UART): Multiprocessor Communications Enable.
0: Logic level of ninth bit is ignored.
1: RI0 is set and an interrupt is generated only when the ninth bit is logic 1.
4 REN0 ^{Receive Enable.}
0: UART0 reception disabled.
1: UART0 reception enabled.
3
TB80 ^{Ninth Transmission Bit.}
The logic level of this bit will be sent as the ninth transmission bit in 9-bit UART Mode
(Mode 1). Unused in 8-bit mode (Mode 0).
2 RB80 ^{Ninth Receive Bit.}
RB80 is assigned the value of the STOP bit in Mode 0; it is assigned the value of the
9th data bit in Mode 1.
1
TI0 ^{Transmit Interrupt Flag.}
Set by hardware when a byte of data has been transmitted by UART0 (after the 8th bit
in 8-bit UART Mode, or at the beginning of the STOP bit in 9-bit UART Mode). When
the UART0 interrupt is enabled, setting this bit causes the CPU to vector to the UART0
interrupt service routine. This bit must be cleared manually by software.
0
RI0 ^{Receive Interrupt Flag.}
Set to 1 by hardware when a byte of data has been received by UART0 (set at the
STOP bit sampling time). When the UART0 interrupt is enabled, setting this bit to 1
causes the CPU to vector to the UART0 interrupt service routine. This bit must be
cleared manually by software.
Rev. 1.3
265