C8051F93X Datasheet, PDF (133/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
P0SKIP
0xD4
0x0 Port 0 Skip
P1
0x90
All Port 1 Latch
P1DRV
0xA5
0xF Port 1 Drive Strength
P1MASK
0xBF
0x0 Port 1 Mask
P1MAT
0xCF
0x0 Port 1 Match
P1MDIN
0xF2
0x0 Port 1 Input Mode Configuration
P1MDOUT
0xA5
0x0 Port 1 Output Mode Configuration
P1SKIP
0xD5
0x0 Port 1 Skip
P2
0xA0
All Port 2 Latch
P2DRV
0xA6
0xF Port 2 Drive Strength
P2MDIN
0xF3
0x0 Port 2 Input Mode Configuration
P2MDOUT
0xA6
0x0 Port 2 Output Mode Configuration
P2SKIP
0xD6
0x0 Port 2 Skip
PCA0CN
0xD8
0x0 PCA0 Control
PCA0CPH0
0xFC
0x0 PCA0 Capture 0 High
PCA0CPH1
0xEA
0x0 PCA0 Capture 1 High
PCA0CPH2
0xEC
0x0 PCA0 Capture 2 High
PCA0CPH3
0xEE
0x0 PCA0 Capture 3 High
PCA0CPH4
0xFE
0x0 PCA0 Capture 4 High
PCA0CPH5
0xD3
0x0 PCA0 Capture 5 High
PCA0CPL0
0xFB
0x0 PCA0 Capture 0 Low
PCA0CPL1
0xE9
0x0 PCA0 Capture 1 Low
PCA0CPL2
0xEB
0x0 PCA0 Capture 2 Low
PCA0CPL3
0xED
0x0 PCA0 Capture 3 Low
PCA0CPL4
0xFD
0x0 PCA0 Capture 4 Low
PCA0CPL5
0xD2
0x0 PCA0 Capture 5 Low
PCA0CPM0
0xDA
0x0 PCA0 Module 0 Mode Register
PCA0CPM1
0xDB
0x0 PCA0 Module 1 Mode Register
PCA0CPM2
0xDC
0x0 PCA0 Module 2 Mode Register
PCA0CPM3
0xDD
0x0 PCA0 Module 3 Mode Register
PCA0CPM4
0xDE
0x0 PCA0 Module 4 Mode Register
PCA0CPM5
0xCE
0x0 PCA0 Module 5 Mode Register
PCA0H
0xFA
0x0 PCA0 Counter High
PCA0L
0xF9
0x0 PCA0 Counter Low
Page
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318
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Rev. 1.3
133