C8051F93X Datasheet, PDF (28/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 3.1. Pin Definitions for the C8051F92x-C8051F93x (Continued)
Name
P0.0
Pin Numbers
Type Description
‘F920/30 ‘F921/31
32
24 D I/O or Port 0.0. See Port I/O Section for a complete description.
A In
V_REF
P0.1
A In
A Out
External V_REF Input.
Internal V_REF Output. External V_REF decoupling capacitors
are recommended. See ADC0 Section for details.
31
23 D I/O or Port 0.1. See Port I/O Section for a complete description.
A In
AGND
P0.2
G Optional Analog Ground. See ADC0 Section for details.
30
22 D I/O or Port 0.2. See Port I/O Section for a complete description.
A In
XTAL1
P0.3
A In External Clock Input. This pin is the external oscillator
return for a crystal or resonator. See Oscillator Section.
29
21 D I/O or Port 0.3. See Port I/O Section for a complete description.
A In
XTAL2
P0.4
A Out
D In
A In
External Clock Output. This pin is the excitation driver for an
external crystal or resonator.
External Clock Input. This pin is the external clock input in
external CMOS clock mode.
External Clock Input. This pin is the external clock input in
capacitor or RC oscillator configurations.
See Oscillator Section for complete details.
28
20 D I/O or Port 0.4. See Port I/O Section for a complete description.
A In
TX
P0.5
D Out UART TX Pin. See Port I/O Section.
27
19 D I/O or Port 0.5. See Port I/O Section for a complete description.
A In
RX
P0.6
D In UART RX Pin. See Port I/O Section.
26
18 D I/O or Port 0.6. See Port I/O Section for a complete description.
A In
CNVSTR
D In External Convert Start Input for ADC0. See ADC0 section
for a complete description.
P0.7
IREF0
25
17 D I/O or Port 0.7. See Port I/O Section for a complete description.
A In
A Out IREF0 Output. See IREF Section for complete description.
*Note: Available only on the C8051F920/30.
28
Rev. 1.3