C8051F93X Datasheet, PDF (266/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 23.2. SBUF0: Serial (UART0) Port Data Buffer
Bit
7
6
5
4
3
2
1
0
Name
SBUF0[7:0]
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0x99
Bit Name
Function
7:0 SBUF0 Serial Data Buffer Bits 7:0 (MSB–LSB).
This SFR accesses two registers; a transmit shift register and a receive latch register.
When data is written to SBUF0, it goes to the transmit shift register and is held for
serial transmission. Writing a byte to SBUF0 initiates the transmission. A read of
SBUF0 returns the contents of the receive latch.
266
Rev. 1.3