C8051F93X Datasheet, PDF(74/330 Page) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93X Datasheet, PDF (74/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93x-C8051F92x

5.2.5. Gain Setting

The ADC has gain settings of 1x and 0.5x. In 1x mode, the full scale reading of the ADC is determined

directly by VREF. In 0.5x mode, the full-scale reading of the ADC occurs when the input voltage is VREF x 2.

The 0.5x gain setting can be useful to obtain a higher input Voltage range when using a small VREF volt-

age, or to measure input voltages that are between VREF and VDD. Gain settings for the ADC are con-

trolled by the AMP0GN bit in register ADC0CF.

5.3. 8-Bit Mode

Setting the ADC08BE bit in register ADC0CF to 1 will put the ADC in 8-bit mode.In 8-bit mode, only the

8 MSBs of data are converted, allowing the conversion to be completed in two fewer SAR clock cycles

than a 10-bit conversion. This can result in an overall lower power consumption since the system can

spend more time in a low power mode. The two LSBs of a conversion are always 00 in this mode, and the

ADC0L register will always read back 0x00.

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Rev. 1.3

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