C8051F93X Datasheet, PDF (25/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
Analog Input Multiplexer
Px.x
VDD
CPT0MD
CP0
Interrupt
CP0
Rising-edge
CP0
Falling-edge
Px.x
Px.x
Px.x
CP0 +
CP0 -
+
-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
(ASYNCHRONOUS)
Reset
Decision
Tree
Interrupt
Logic
CP0
Crossbar
CP0A
Figure 1.9. Comparator 0 Functional Block Diagram
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
Analog Input Multiplexer
Px.x
VDD
CPT0MD
CP1
Interrupt
CP1
Rising-edge
CP1
Falling-edge
Px.x
Px.x
Px.x
CP1 +
CP1 -
+
-
GND
D ^SET Q
Q CLR
D ^SET Q
Q CLR
(SYNCHRONIZER)
(ASYNCHRONOUS)
Reset
Decision
Tree
Interrupt
Logic
CP1
Crossbar
CP1A
Figure 1.10. Comparator 1 Functional Block Diagram
Rev. 1.3
25