C8051F93X Datasheet, PDF (160/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
14.1. Normal Mode
The MCU is fully functional in Normal Mode. Figure 14.1 shows the on-chip power distribution to various
peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+, and
the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are always powered directly from the
VBAT pin. All analog peripherals are directly powered from the VDD/DC+ pin, which is an output in one-cell
mode and an input in two-cell mode. All digital peripherals and the CIP-51 core are powered from the 1.8 V
internal core supply. The RAM is also powered from the core supply in Normal mode.
VBAT ^{One-cell: 0.9 to 1.8 V} VDD/DC+
Two-cell: 1.8 to 3.6 V
One-cell or Two-cell: 1.8 to 3.6 V
1.9 V
typical
DC0
Note: VDD/DC+ must be > VBAT _GPIO
One-Cell Active/
Idle/Stop/Suspend
One-Cell Sleep
Analog Peripherals
A
M
U
VREG0 ^X
VREF
10-bit
300 ksps
ADC
TEMP
SENSOR
IREF0
+
+
-
-
VOLTAGE
COMPARATORS
Sleep
Active/Idle/
Stop/Suspend _{1.8 V} Digital Peripherals
PMU0
CIP-51
Core
Flash
UART
SPI
SmaRTClock
RAM
Timers
SMBus
Figure 14.1. C8051F93x-C8051F92x Power Distribution
160
Rev. 1.3