C8051F93X Datasheet, PDF(114/330 Page) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93X Datasheet, PDF (114/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

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C8051F93x-C8051F92x

9.2. Data Memory

The C8051F93x-C8051F92x device family includes 4352 bytes of RAM data memory. 256 bytes of this

memory is mapped into the internal RAM space of the 8051. 4096 bytes of this memory is on-chip âexter-

nalâ memory. The data memory map is shown in Figure 9.1 for reference.

9.2.1. Internal RAM

There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The

lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either

direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00

through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight

byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or

as 128 bit locations accessible with the direct addressing mode.

The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the

same address space as the Special Function Registers (SFR) but is physically separate from the SFR

space. The addressing mode used by an instruction when accessing locations above 0x7F determines

whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use

direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the

upper 128 bytes of data memory. Figure 9.1 illustrates the data memory organization of the C8051F93x-

C8051F92x.

9.2.1.1. General Purpose Registers

The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of gen-

eral-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7. Only

one of these banks may be enabled at a time. Two bits in the program status word, RS0 (PSW.3) and RS1

(PSW.4), select the active register bank (see description of the PSW in SFR Definition 8.6). This allows

fast context switching when entering subroutines and interrupt service routines. Indirect addressing modes

use registers R0 and R1 as index registers.

9.2.1.2. Bit Addressable Locations

In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20

through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from

0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address

0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by

the type of instruction used (bit source or destination operands as opposed to a byte source or destina-

tion).

The MCS-51â¢ assembly language allows an alternate notation for bit addressing of the form XX.B where

XX is the byte address and B is the bit position within the byte. For example, the instruction:

MOV C, 22.3h

moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.

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Rev. 1.3

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