C8051F93X Datasheet, PDF (130/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
11.1. SFR Paging
To accommodate more than 128 SFRs in the 0x80 to 0xFF address space, SFR paging has been
implemented. By default, all SFR accesses target SFR Page 0x0 to allow access to the registers listed in
Table 11.1. During device initialization, some SFRs located on SFR Page 0xF may need to be accessed.
Table 11.2 lists the SFRs accessible from SFR Page 0x0F. Some SFRs are accessible from both pages,
including the SFRPAGE register. SFRs accessible only from Page 0xF are in bold.
The following procedure should be used when accessing SFRs from Page 0xF:
Step 1. Save the current interrupt state (EA_save = EA).
Step 2. Disable Interrupts (EA = 0).
Step 3. Set SFRPAGE = 0xF.
Step 4. Access the SFRs located on SFR Page 0xF.
Step 5. Set SFRPAGE = 0x0.
Step 6. Restore interrupt state (EA = EA_save).
Table 11.2. Special Function Register (SFR) Memory Map (Page 0xF)
F8
F0 B
E8
E0 ACC
D8
D0 PSW
C8
C0
B8
ADC0PWR
B0
A8 IE
CLKSEL
A0 P2
98
90 P1 CRC0DAT CRC0CN
88
80 P0
SP
DPL
0(8)
1(9)
2(A)
(bit addressable)
CRC0IN
DPH
3(B)
P0DRV
4(C)
EIP1
EIE1
EIP2
EIE2
ADC0TK
P1DRV
P2DRV SFRPAGE
CRC0FLIP CRC0AUTO CRC0CNT
TOFFL
5(D)
TOFFH
6(E)
PCON
7(F)
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Rev. 1.3