C8051F93X Datasheet, PDF (79/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
Bit
7
6
5
4
3
2
1
0
Name
AD0TK[5:0]
Type
R
R
R/W
Reset
0
0
0
1
0
1
1
0
SFR Page = 0xF; SFR Address = 0xBD
Bit Name
Function
7:6 Unused Unused.
Read = 00b; Write = Don’t Care.
5:0 AD0TK[5:0] ADC0 Burst Mode Track Time.
Sets the time delay between consecutive conversions performed in Burst Mode.
The ADC0 Burst Mode Track time is programmed according to the following 
equation:
AD0TK = 63 – _^T---5-^t--0^r---^a-_n--^c-_s--^k- – 1_
or
Ttrack = 64 – AD0TK50ns
Notes:If AD0TM is set to 1, an additional 3 SAR clock cycles of Track time will be inserted prior to starting the
conversion.
The Burst Mode Track delay is not inserted prior to the first conversion. The required tracking time for the first
conversion should be met by the Burst Mode Power-Up Time.
Rev. 1.3
79