C8051F93X Datasheet, PDF (134/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
PCA0MD
0xD9
0x0 PCA0 Mode
PCA0PWM
0xDF
0x0 PCA0 PWM Configuration
PCON
0x87
0x0 Power Control
PMU0CF
0xB5
0x0 PMU0 Configuration
PSCTL
0x8F
0x0 Program Store R/W Control
PSW
0xD0
All Program Status Word
REF0CN
0xD1
0x0 Voltage Reference Control
REG0CN
0xC9
0x0 Voltage Regulator (VREG0) Control
RSTSRC
0xEF
0x0 Reset Source Configuration/Status
RTC0ADR
0xAC
0x0 RTC0 Address
RTC0DAT
0xAD
0x0 RTC0 Data
RTC0KEY
0xAE
0x0 RTC0 Key
SBUF0
0x99
0x0 UART0 Data Buffer
SCON0
0x98
0x0 UART0 Control
SFRPAGE
0xA7
All SFR Page
SMB0ADM
0xF5
0x0 SMBus Slave Address Mask
SMB0ADR
0xF4
0x0 SMBus Slave Address
SMB0CF
0xC1
0x0 SMBus0 Configuration
SMB0CN
0xC0
0x0 SMBus0 Control
SMB0DAT
0xC2
0x0 SMBus0 Data
SP
0x81
All Stack Pointer
SPI0CFG
0xA1
0x0 SPI0 Configuration
SPI0CKR
0xA2
0x0 SPI0 Clock Rate Control
SPI0CN
0xF8
0x0 SPI0 Control
SPI0DAT
0xA3
0x0 SPI0 Data
SPI1CFG
0x84
0x0 SPI1 Configuration
SPI1CKR
0x85
0x0 SPI1 Clock Rate Control
SPI1CN
0xB0
0x0 SPI1 Control
SPI1DAT
0x86
0x0 SPI1 Data
TCON
0x88
0x0 Timer/Counter Control
TH0
0x8C
0x0 Timer/Counter 0 High
TH1
0x8D
0x0 Timer/Counter 1 High
TL0
0x8A
0x0 Timer/Counter 0 Low
TL1
0x8B
0x0 Timer/Counter 1 Low
134
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