C8051F93X Datasheet, PDF (231/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 21.10. P0MDIN: Port0 Input Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDIN[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page= 0x0; SFR Address = 0xF1
Bit
Name
Function
7:0 P0MDIN[7:0] Analog Configuration Bits for P0.7–P0.0 (respectively).
Port pins configured for analog mode have their weak pullup, and digital receiver
disabled. The digital driver is not explicitly disabled.
0: Corresponding P0.n pin is configured for analog mode.
1: Corresponding P0.n pin is not configured for analog mode.
SFR Definition 21.11. P0MDOUT: Port0 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P0MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA4
Bit
Name
Function
7:0 P0MDOUT[7:0] Output Configuration Bits for P0.7–P0.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P0MDIN is logic 0.
0: Corresponding P0.n Output is open-drain.
1: Corresponding P0.n Output is push-pull.
Rev. 1.3
231