C8051F93X Datasheet, PDF (237/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 21.21. P2MDOUT: Port2 Output Mode
Bit
7
6
5
4
3
2
1
0
Name
P2MDOUT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xA6
Bit
Name
Function
7:0 P2MDOUT[7:0] Output Configuration Bits for P2.7–P2.0 (respectively).
These bits control the digital driver even when the corresponding bit in register
P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
SFR Definition 21.22. P2DRV: Port2 Drive Strength
Bit
7
6
5
4
3
2
1
0
Name
P2DRV[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0F; SFR Address = 0xA6
Bit
Name
Function
7:0 P2DRV[7:0] Drive Strength Configuration Bits for P2.7–P2.0 (respectively).
Configures digital I/O Port cells to high or low output drive strength.
0: Corresponding P2.n Output has low output drive strength.
1: Corresponding P2.n Output has high output drive strength.
Note: Pins P2.0-P2.6 are only available in 32-pin devices.
Rev. 1.3
237