C8051F93X Datasheet, PDF (298/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 25.11. TMR2L: Timer 2 Low Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR2L[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCC
Bit Name
Function
7:0 TMR2L[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2L register contains the low byte of the 16-bit Timer 2. In 8-
bit mode, TMR2L contains the 8-bit low byte timer value.
SFR Definition 25.12. TMR2H Timer 2 High Byte
Bit
7
6
5
4
3
2
1
0
Name
TMR2H[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0x0; SFR Address = 0xCD
Bit Name
Function
7:0 TMR2H[7:0] Timer 2 Low Byte.
In 16-bit mode, the TMR2H register contains the high byte of the 16-bit Timer 2. In 8-
bit mode, TMR2H contains the 8-bit high byte timer value.
298
Rev. 1.3