C8051F93X Datasheet, PDF (40/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Figure 3.9. QFN-24 Package Drawing
Table 3.4. QFN-24 Package Dimensions
Dimension Min
Typ
Max
A
0.70 0.75 0.80
Dimension Min
Typ
Max
L
0.30 0.40 0.50
A1
0.00 0.02 0.05
b
0.18 0.25 0.30
L1
0.00
—
0.15
aaa
—
—
0.15
D
4.00 BSC
D2
2.55 2.70 2.80
bbb
—
—
0.10
ddd
—
—
0.05
e
0.50 BSC
eee
—
—
0.08
E
4.00 BSC
E2
2.55 2.70 2.80
Z
—
0.24
—
Y
—
0.18
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation WGGD except
for custom features D2, E2, Z, Y, and L which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small
Body Components.
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Rev. 1.3