C8051F93X Datasheet, PDF (76/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bit
7
6
5
4
3
2
1
0
Name
Type
AD0SC[4:0]
R/W
AD08BE
R/W
AD0TM
R/W
AMP0GN
R/W
Reset
1
1
1
1
1
0
0
0
SFR Page = 0x0; SFR Address = 0xBC
Bit Name
Function
7:3 AD0SC[4:0] ADC0 SAR Conversion Clock Divider.
SAR Conversion clock is derived from FCLK by the following equation, where
AD0SC refers to the 5-bit value held in bits AD0SC[4:0]. SAR Conversion clock
requirements are given in Table 4.9.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is the 20 MHz low power oscillator, independent of the system
clock.
AD0SC = ---^F----^C----^L----^K---- – 1 *
CLK_SAR
*Round the result up.
or
CLK_SAR
=
-------^F----^C----^L----^K---------
AD0SC + 1
2
AD08BE ADC0 8-Bit Mode Enable.
0: ADC0 operates in 10-bit mode (normal operation).
1: ADC0 operates in 8-bit mode.
1
AD0TM ADC0 Track Mode.
Selects between Normal or Delayed Tracking Modes.
0: Normal Track Mode: When ADC0 is enabled, conversion begins immediately following the
start-of-conversion signal.
1: Delayed Track Mode: When ADC0 is enabled, conversion begins 3 SAR clock cycles fol-
lowing the start-of-conversion signal. The ADC is allowed to track during this time.
0 AMP0GN ADC0 Gain Control.
0: The on-chip PGA gain is 0.5.
1: The on-chip PGA gain is 1.
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Rev. 1.3