C8051F93X Datasheet, PDF (153/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
13.5. Flash Write and Erase Guidelines
Any system which contains routines which write or erase Flash memory from software involves some risk
that the write or erase routines will execute unintentionally if the CPU is operating outside its specified
operating range of VDD, system clock frequency, or temperature. This accidental execution of Flash modi-
fying code can result in alteration of Flash memory contents causing a system failure that is only recover-
able by re-Flashing the code in the device.
To help prevent the accidental modification of Flash by firmware, the VDD Monitor must be enabled and
enabled as a reset source on C8051F92x-C8051F93x devices for the Flash to be successfully modified. If
either the VDD Monitor or the VDD Monitor reset source is not enabled, a Flash Error Device Reset
will be generated when the firmware attempts to modify the Flash.
The following guidelines are recommended for any system that contains routines which write or erase
Flash from code.
13.5.1. VDD Maintenance and the VDD Monitor
1. If the system power supply is subject to voltage or current "spikes," add sufficient transient
protection devices to the power supply to ensure that the supply voltages listed in the Absolute
Maximum Ratings table are not exceeded.
2. Make certain that the maximum VBAT ramp time specification of 3 ms is met. This specifica-
tion is outlined in Table 4.4 on page 59. On silicon revision F and later revisions, if the system
cannot meet this rise time specification, then add an external VDD brownout circuit to the RST
pin of the device that holds the device in reset until VDD reaches the minimum device operat-
ing voltage and re-asserts RST if VDD drops below the minimum device operating voltage.
3. Keep the on-chip VDD Monitor enabled and enable the VDD Monitor as a reset source as
early in code as possible. This should be the first set of instructions executed after the Reset
Vector. For C-based systems, this will involve modifying the startup code added by the 'C'
compiler. See your compiler documentation for more details. Make certain that there are no
delays in software between enabling the VDD Monitor and enabling the VDD Monitor as a
reset source. Code examples showing this can be found in “AN201: Writing to Flash from
Firmware," available from the Silicon Laboratories web site.
Notes: 
On C8051F93x-C8051F92x devices, both the VDD Monitor and the VDD Monitor reset source
must be enabled to write or erase Flash without generating a Flash Error Device Reset.
On C8051F93x-C8051F92x devices, both the VDD Monitor and the VDD Monitor reset source
are enabled by hardware after a power-on reset.
4. As an added precaution, explicitly enable the VDD Monitor and enable the VDD Monitor as a
reset source inside the functions that write and erase Flash memory. The VDD Monitor enable
instructions should be placed just after the instruction to set PSWE to a '1', but before the
Flash write or erase operation instruction.
5. Make certain that all writes to the RSTSRC (Reset Sources) register use direct assignment
operators and explicitly DO NOT use the bit-wise operators (such as AND or OR). For exam-
ple, "RSTSRC = 0x02" is correct, but "RSTSRC |= 0x02" is incorrect.
6. Make certain that all writes to the RSTSRC register explicitly set the PORSF bit to a '1'. Areas
to check are initialization code which enables other reset sources, such as the Missing Clock
Detector or Comparator, for example, and instructions which force a Software Reset. A global
search on "RSTSRC" can quickly verify this.
Rev. 1.3
153