C8051F93X Datasheet, PDF (172/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 15.2. CRC0IN: CRC0 Data Input
Bit
7
6
5
4
3
2
1
0
Name
CRC0IN[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x93
Bit
Name
Function
7:0 CRC0IN[7:0] CRC0 Data Input.
Each write to CRC0IN results in the written data being computed into the existing
CRC result according to the CRC algorithm described in Section 15.1
SFR Definition 15.3. CRC0DAT: CRC0 Data Output
Bit
7
6
5
4
3
2
1
0
Name
CRC0DAT[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page = 0xF; SFR Address = 0x91
Bit
Name
Function
7:0 CRC0DAT[7:0] CRC0 Data Output.
Each read or write performed on CRC0DAT targets the CRC result bits pointed to
by the CRC0 Result Pointer (CRC0PNT bits in CRC0CN).
172
Rev. 1.3