C8051F93X Datasheet, PDF (228/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
SFR Definition 21.6. P1MASK: Port1 Mask Register
Bit
7
6
5
4
3
2
1
0
Name
P1MASK[7:0]
Type
R/W
Reset
0
0
0
0
0
0
0
0
SFR Page= 0x0; SFR Address = 0xBF
Bit
Name
Function
7:0 P1MASK[7:0] Port 1 Mask Value.
Selects P1 pins to be compared to the corresponding bits in P1MAT.
0: P1.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P1.n pin logic value is compared to P1MAT.n.
Note: On C8051F931/21 devices, port match is not available on P1.6 or P1.7. The corresponding P1MASK bits
must be set to 0b.
SFR Definition 21.7. P1MAT: Port1 Match Register
Bit
7
6
5
4
3
2
1
0
Name
P1MAT[7:0]
Type
R/W
Reset
1
1
1
1
1
1
1
1
SFR Page = 0x0; SFR Address = 0xCF
Bit
Name
Function
7:0 P1MAT[7:0] Port 1 Match Value.
Match comparison value used on Port 1 for bits in P1MASK which are set to 1.
0: P1.n pin logic value is compared with logic LOW.
1: P1.n pin logic value is compared with logic HIGH.
Note: On C8051F931/21 devices, port match is not available on P1.6 or P1.7.
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Rev. 1.3