C8051F93X Datasheet, PDF (112/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
9. Memory Organization
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are
two separate memory spaces: program memory and data memory. Program and data memory share the
same address space but are accessed via different instruction types. The memory organization of the
C8051F93x-C8051F92x device family is shown in Figure 9.1
PROGRAM/DATA MEMORY
(FLASH)
C8051F930/1
0x03FF
0x0000
0xFFFF
0xFC00
0xFBFF
Scrachpad Memory
(DATA only)
RESERVED
64KB FLASH
(In-System
Programmable in 1024
Byte Sectors)
DATA MEMORY
(R A M )
INTERNAL DATA ADDRESS SPACE
Upper 128 RAM
(Indirect Addressing Only)
Special Function
Registers
(Direct Addressing Only)
0
F
(Direct and Indirect
Addressing)
Bit Addressable
General Purpose
R e g is te rs
Lower 128 RAM
(Direct and Indirect
Addressing)
0x0000
0x03FF
0x0000
C8051F920/1
Scrachpad Memory
(DATA only)
0x7FFF
32KB FLASH
(In-System
Programmable in 1024
Byte Sectors)
0x0000
EXTERNAL DATA ADDRESS SPACE
0x1FFF
0x1000
0x0FFF
Off-chip XRAM space
(only available on 32-pin
devices)
XRAM - 4096 Bytes
(accessable using MOVX
instruction)
0x0000
Figure 9.1. C8051F93x-C8051F92x Memory Map
112
Rev. 1.3