C8051F93X Datasheet, PDF (132/330 Pages) Silicon Laboratories – Pipelined intstruction architecture executes 70 of instruction in 1 or 2 system clocks

C8051F93x-C8051F92x
Table 11.3. Special Function Registers (Continued)
SFRs are listed in alphabetical order. All undefined SFR locations are reserved
Register
Address SFR Page
Description
CPT1MD
0x9C
0x0 Comparator1 Mode Selection
CPT1MX
0x9E
0x0 Comparator1 Mux Selection
CRC0AUTO
0x96
0xF CRC0 Automatic Control
CRC0CN
0x92
0xF CRC0 Control
CRC0CNT
0x97
0xF CRC0 Automatic Flash Sector Count
CRC0DAT
0x91
0xF CRC0 Data
CRC0FLIP
0x95
0xF CRC0 Flip
CRC0IN
0x93
0xF CRC0 Input
DC0CF
0x96
0x0 DC0 (DC-DC Converter) Configuration
DC0CN
0x97
0x0 DC0 (DC-DC Converter) Control
DPH
0x83
All Data Pointer High
DPL
0x82
All Data Pointer Low
EIE1
0xE6
All Extended Interrupt Enable 1
EIE2
0xE7
All Extended Interrupt Enable 2
EIP1
0xF6
0x0 Extended Interrupt Priority 1
EIP2
0xF7
0x0 Extended Interrupt Priority 2
EMI0CF
0xAB
0x0 EMIF Configuration
EMI0CN
0xAA
0x0 EMIF Control
EMI0TC
0xAF
0x0 EMIF Timing Control
FLKEY
0xB7
0x0 Flash Lock And Key
FLSCL
0xB6
0x0 Flash Scale
IE
0xA8
All Interrupt Enable
IP
0xB8
0x0 Interrupt Priority
IREF0CN
0xB9
0x0 Current Reference IREF Control
IT01CF
0xE4
0x0 INT0/INT1 Configuration
OSCICL
0xB3
0x0 Internal Oscillator Calibration
OSCICN
0xB2
0x0 Internal Oscillator Control
OSCXCN
0xB1
0x0 External Oscillator Control
P0
0x80
All Port 0 Latch
P0DRV
0xA4
0xF Port 0 Drive Strength
P0MASK
0xC7
0x0 Port 0 Mask
P0MAT
0xD7
0x0 Port 0 Match
P0MDIN
0xF1
0x0 Port 0 Input Mode Configuration
P0MDOUT
0xA4
0x0 Port 0 Output Mode Configuration
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